In electronic instrumentation and signal processing, a time to digital converter (TDC) is a device that recognizes events and provides a digital representation of the time when an event occurred. A TDC can output a time of arrival for an incoming pulse. Some applications of TDC may measure the time interval between two events rather than some specific event in absolute time. Two delay lines are usually used to measure the fine interval between the rising edges of the start and stop signals. The simplest arrangement is a tapped delay line with one D flip-flop (DFF) connected to each tap. In this case, the resolution is the propagation delay of a single delay buffer. Higher resolution can be obtained by utilizing a Vernier delay line (VDL) using two delay buffer chains. Timing resolution is determined by the difference between two propagation delay values.
Typically, Vernier time to digital conversion circuits utilize an additional delay line disposed along the propagation path of the reference clock for sampling the input signal. The delay line for the reference clock reacts faster than the delay line for the input signal. Thus, in a Vernier time to digital converter, the input signal travels through a slower delay path and is sampled by a reference clock signal that travels through a faster delay path. By shifting the rising edge of the reference clock signal due to the faster delay path, improved phase quantization can be obtained compared to traditional time to digital converters. The phase quantization is proportional to the difference in the delays between the two delay lines. Maintaining a consistent designed difference in the delays of the two delays lines is critical to proper and accurate operation.
Although more accurate for TDC, drawbacks with the use of TDC based on Vernier delay technique include complexity of the circuitry and the effect of variations in process voltage and temperature (PVT). Therefore, it is desirable to provide new methods and apparatuses for a Vernier delay line TDC that can automatically adjust delay to achieve a fixed ratio delay time between slow buffers and fast buffers of a system independent of PVT and has less complexity than previous Vernier time to digital convertors.